IDT Announces World’s Lowest-power PCI Express Timing Family
The IDT 9FGVxxxx (synthesizers) and 9DBVxxxx (buffers) are the latest members of IDT’s leading portfolio of PCI Express solutions, which also includes switches, bridges, signal repeaters, flash controllers and timing. The new timing devices consume less than 50 mW of power – less than one-tenth the power required by previous solutions. The ultra-low power consumption reduces heat dissipation to ease cooling requirements in large-scale cloud computing applications, resulting in a typical datacenter energy cost saving of over $600 per rack per year.
“As the leaders in timing and PCI Express switching solutions, IDT’s expert engineering teams worked in concert to develop the best solution for PCI Express timing,” said Fred Zust, vice president and general manager of the Timing and Synchronization Division at IDT. “We understand that our customers want the highest level of performance with the lowest power consumption, and that’s exactly what our new family of devices delivers. Combined with our low-power PCIe® switches and flash controllers, IDT offers the most competitive and complete PCIe solution on the market.”
The new clock synthesizers and buffers are available with either integrated or external termination on the differential outputs. External termination provides designers maximum flexibility when working in a non-homogenous timing environment. Conversely, internal termination provides the most space savings and lowest discrete component count when working in a homogenous timing environment with 100 ohm differential transmission lines. All members of the new PCI Express timing family meet PCIe Gen 1, Gen 2, and Gen 3 performance requirements, allowing for long-lifecycle designs that customers can re-use through several generations of their products.
Most members of the new timing family feature a selectable SMBus address so that multiple devices can seamlessly share the same SMBus segment without the cumbersome additional logic that is often required with other solutions. Each differential output features an output enable (OE#) pin, providing system designers with the flexibility required for advanced power management schemes. In addition, the devices feature SMBus-configurable differential slew rate for each output and SMBus-configurable differential amplitude for signal integrity tuning. The new synthesizers and buffers are currently offered in 2-, 4- and 8-output variants. Additional functions and output variants are under development.
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