Toshiba Unveils Intellectual-Property Block
Toshiba Electronics Europe's ASIC and Foundry Business Unit has announced an intellectual-property (IP) block for the rapid integration of USB functionality into system-on-chip (SoC) designs. Delivering physical layer functionality for USB 2.0, the Toshiba USB 2.0 PHY IP provides a silicon-proven interface between the USB host or device controller and the USB system. The PHY provides all the functionality needed to process the USB protocol and the physical layer signalling for USB 2.0 high-speed (HS) 480Mbps operation, as well as USB 1.1 full-speed (FS) transmission at 12Mbps and low-speed (LS) transmission at 1.5Mbps. SYNC detection, parallel-to-serial and serial-to-parallel data conversion and data recovery are all supported. Toshiba's IP comprises a transceiver module, a common PLL/bias block, digital control logic and 'on-the-go' (OTG) functionality. The common block includes an internal clock generator for accurate HS data transmission. The integrated PLL can o...