Synopsys Introduces Galaxy Constraint Analyzer
Synopsys has unveiled the Galaxy Constraint Analyzer tool, which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer enables designers to quickly assess the correctness and consistency of timing constraints. Correctness and consistency lead to more efficient runtimes in Synopsys's Design Compiler synthesis and IC Compiler physical implementation tools, according to the company. The Galaxy Constraint Analyzer features constraint debug capabilities to help designers eliminate long 'trial-and-error iterations' during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip sign-off.
Hitoshi Sugihara, department manager of the DFM and Digital EDA Technology Development Department in the Design Technology Division of Renesas Technology Corporation, said: 'Our complex SoC [system-on-chip] designs have a large number of clocks that require an intricate set of timing constraint definitions. 'Making sure that our design engineers start with and hand off a high-quality set of constraint files significantly lowers risk to our design schedules. 'Using the Galaxy Constraint Analyzer enabled us to find constraint issues that we could not have found otherwise, saving us significant time and effort.
'We plan to incorporate the Galaxy Constraint Analyzer into our standard design flow that includes Design Compiler and IC Compiler,' he added. The rapid increase in design size and complexity, as well as the widespread reuse of intellectual-property (IP) design blocks, has led to a major increase in the size and complexity of timing constraint specification files. Synopsys claims that ensuring high-quality timing constraints is paramount to efficient design implementation, especially during hand-offs between teams. Incomplete, inconsistent or conflicting constraints can cause optimisation and implementation tools to run ineffectively or to never converge.
To address this challenge, the Galaxy Constraint Analyzer tool provides an extensive set of rule checks designed to maximise the efficiency of Design Compiler synthesis and IC Compiler physical implementation. In addition, the Galaxy Constraint Analyzer uses technology based on Synopsys's golden Primetime timing engine to ensure the correct interpretation and propagation of constraints.
This gives designers a sign-off-correlated view of the constraints ahead of each step of the design implementation process. The Galaxy Constraint Analyzer's ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a set of interactive analysis and debug capabilities, is intended to help designers quickly identify and fix constraint issues within hours, rather than days. Synopsys is a specialist in software and IP for semiconductor design, verification and manufacturing.
Synopsys has unveiled the Galaxy Constraint Analyzer tool, which improves designer productivity through look-ahead constraint analysis technology tuned for the Synopsys Galaxy Implementation Platform. The Galaxy Constraint Analyzer enables designers to quickly assess the correctness and consistency of timing constraints. Correctness and consistency lead to more efficient runtimes in Synopsys's Design Compiler synthesis and IC Compiler physical implementation tools, according to the company. The Galaxy Constraint Analyzer features constraint debug capabilities to help designers eliminate long 'trial-and-error iterations' during implementation, reducing design cost as a result of more predictable schedules all the way to full-chip sign-off.
Hitoshi Sugihara, department manager of the DFM and Digital EDA Technology Development Department in the Design Technology Division of Renesas Technology Corporation, said: 'Our complex SoC [system-on-chip] designs have a large number of clocks that require an intricate set of timing constraint definitions. 'Making sure that our design engineers start with and hand off a high-quality set of constraint files significantly lowers risk to our design schedules. 'Using the Galaxy Constraint Analyzer enabled us to find constraint issues that we could not have found otherwise, saving us significant time and effort.
'We plan to incorporate the Galaxy Constraint Analyzer into our standard design flow that includes Design Compiler and IC Compiler,' he added. The rapid increase in design size and complexity, as well as the widespread reuse of intellectual-property (IP) design blocks, has led to a major increase in the size and complexity of timing constraint specification files. Synopsys claims that ensuring high-quality timing constraints is paramount to efficient design implementation, especially during hand-offs between teams. Incomplete, inconsistent or conflicting constraints can cause optimisation and implementation tools to run ineffectively or to never converge.
To address this challenge, the Galaxy Constraint Analyzer tool provides an extensive set of rule checks designed to maximise the efficiency of Design Compiler synthesis and IC Compiler physical implementation. In addition, the Galaxy Constraint Analyzer uses technology based on Synopsys's golden Primetime timing engine to ensure the correct interpretation and propagation of constraints.
This gives designers a sign-off-correlated view of the constraints ahead of each step of the design implementation process. The Galaxy Constraint Analyzer's ability to deliver comprehensive constraint analysis on 10-million-gate designs in a matter of minutes, combined with a set of interactive analysis and debug capabilities, is intended to help designers quickly identify and fix constraint issues within hours, rather than days. Synopsys is a specialist in software and IP for semiconductor design, verification and manufacturing.
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